1. Field of the Invention
The present invention relates to a semiconductor device, a test method of a semiconductor device, and a system including the semiconductor device.
2. Description of the Related Art
Semiconductor devices having a storage function, e.g., semiconductor memory devices, have been developed so as to increase the degree of integration and the capacity. One of techniques for increasing the degree of integration and the capacity includes stacking a plurality of chips (memory chips) on an I/O chip and connecting the plurality of chips stacked on the I/O chip to each other via through electrodes (TSV: through silicon via), which penetrate the chips in the thickness direction thereof (Patent Document 1: US 2004/0257847 A1). Another technique is a dual die package (DDP) technique in which two chips having the same structure (i.e., two memory dies) are stacked in one package (Patent Document 2: US 2006/0126404 A1).
Meanwhile, an operation test of examining whether all of memory cells correctly work in a semiconductor memory device is required to be performed after packaging (assembly process) in which chips are sealed by molding or the like before the shipment of the semiconductor memory device. As the storage capacity increases, the operation test needs more time. Therefore, it has been desired to shorten a period of an operation test (test period).
An I/O compression test function mounted on a single chip has been used in order to reduce not only a period of an operation test, but also the number of drives and comparators in a tester device, which is a tool for examining a semiconductor device, or in a controller mounted on a motherboard for controlling a semiconductor device. Drivers are means for writing data in memory cells of a semiconductor device from a tester device via TSVs of the semiconductor device during an operation test. Comparators are means for judging, during the operation test, whether signal outputs (logics of signals) that have been read from the memory cells and transmitted to the exterior of the semiconductor device via the TSVs identical with expectations of the tester device. Furthermore, the I/O compression test function is a function of simultaneously inputting (writing) data into a plurality of I/O lines (internal data buses) of each chip from a specific I/O terminal of a plurality of I/O terminals in a semiconductor device and outputting the logical AND of the data of the I/O lines to the specific I/O terminal.
Patent Document 3 (JP-A 9-259600) discloses this type of operation test time-reduction technique, in which a chip has a data compression test mode of compressing reading data and outputting the compressed data.